Memories, such as random access memory (RAM), for example, or static or dynamic RAM, may take up considerable space in a system and may dominate power consumption of the system.
In order to maximize power efficiency, a large word memory architecture may be implemented. A large word memory architecture may be one in which multiple bits corresponding to a larger sized word are written to the memory simultaneously. For example, in some systems, the large word may be 32, 64, 128 or 256 bits.
Although the use of large words may increase bandwidth and reduce power consumption, allowance may be made for partial writes to fewer bits corresponding to a word size smaller than the large word.
Standard macrocell memory may implement large word sizes. In standard macrocell memory, write operations are performed through pass gates in a sense amplifier using differential data lines. The sense amplifiers may be switched by an enable signal to connect bit lines to charged differential data lines indicating the value to be written. For example, when the differential data or write lines have been charged, an enable signal switches a pass gate transistor for each sense amplifier to connect the differential data or write line to a differential bit line for that sense amplifier column. These memories may have a low swing data transfer. They may also provide very large words—typically 256 bit words.
In order to perform partial write operations for standard macrocell memory, a large word may be fetched from the memory and stored in a cache memory, a read/write operation may be carried out on parts of the large word stored in the cache memory, and the large word may be written back into the memory. In this manner, several operations, including fetch/modify/writeback operations, are carried out for a partial write.
The standard macrocell may therefore be more suited to systems where there is a low frequency in pure random operations such as partial writes.
Pure random macrocells may perform a write operation on a gate of a transistor placed in the sense amplifier. The transistor may behave as a switch, switching on and off according to a data signal connected to its gate terminal. The data line may be a full swing data line so that the information is transferred to the gate. In this manner, a bit by bit partial write becomes possible on the differential data lines: when no write operation is required on a particular data bit (in case of partial write), keeping both write lines at zero ensures that memory data will not be altered. This may enable the implementation of small word sizes—for example, 32 to 128 bit words.
In contrast to the standard macrocell, pure random macrocells may carry out a partial write in one cycle and may therefore be more suited to operations where there is a high frequency of partial writes. Pure random macrocell memory, however, may have high power consumption due to data line buffers leakage and dynamic consumption related to full swing operation.